Huawei Ascend 950/950DT Deep Dive: China's First System-Level AI Chip Breakthrough to Rival NVIDIA H200

Huawei Ascend 950/950DT Deep Dive: China’s First System-Level AI Chip Breakthrough to Rival NVIDIA H200

1. Introduction: A Historic Week

On August 1, 2026, Huawei announced the successful tape-out of the Ascend 950 AI chip on its first attempt. Six days later—August 7—the upgraded 950DT variant went live four months ahead of schedule. In the same week, the American Enterprise Institute (AEI) published a report acknowledging that Huawei could meet one-third to one-half of China’s AI computing demand by 2028.

This is not an incremental iteration. It is a system-level capability leap.

From a single-card FP16 peak performance of 1.6 PFLOPS (surpassing NVIDIA H200’s 1.2 PFLOPS), to the self-developed HiZQ 2.0 memory delivering 4 TB/s bandwidth, to the 8,192-chip Atlas 950 SuperPoD—the Ascend 950 series marks the first time a Chinese AI chip has achieved competitive capability against NVIDIA at the system level. This system-level breakthrough means far more than surpassing single-card performance numbers; it represents full-stack autonomous control spanning chip design, fabrication, packaging, memory technology, interconnect communication, cluster scheduling, and software ecosystem.

This article provides a deep technical analysis of the Ascend 950PR and 950DT architectures, core innovations, and engineering implementations, accompanied by complete, runnable code to help readers understand this milestone product from hardware simulation to cluster scheduling.

2. One Die, Two Chips: The “Scenario-Based Nuclear Fission” of PR and DT

2.1 Why Two Chips?

Large model inference consists of two fundamentally different phases:

• Prefill (Pre-fill): Processes the entire user input prompt at once, building KV cache in parallel. This phase is compute-intensive, prioritizing raw compute power with relatively low bandwidth requirements.
• Decode: Generates responses one token at a time, repeatedly reading and writing KV cache. This phase is memory-intensive, prioritizing bandwidth and capacity.

Running both phases on the same chip is like asking a sprinter to run a marathon—suboptimal in both directions. In traditional single-chip solutions, Prefill leaves memory bandwidth idle while Decode chokes on bandwidth but leaves compute resources underutilized.

Huawei’s approach is “one die, two chips”: the same 950 core die paired with different self-developed high-bandwidth memory solutions, precisely matching each phase’s requirements.

2.2 Core Parameter Comparison

2.3 DaVinci 3.0 Architecture Deep Dive

The DaVinci 3.0 architecture continues the three-compute-unit design of previous Ascend generations, but each unit has been deeply optimized for large model training scenarios.

2.3.1 The Three Compute Units

Cube Unit (Matrix Compute Core): This is the compute density champion of the Ascend chip. The 3D Cube uses a 16×16×16 systolic array design, capable of 4,096 multiply-accumulate operations per instruction cycle. At FP8 precision, each Cube unit outputs 1,024 results per cycle; at MXFP4, 2,048 results. The 950DT integrates 64 AI Cores, each containing a complete Cube unit.

Vector Unit (Vector Parallel Engine): The SIMD width has been expanded from 256 bits in the previous generation to 512 bits. A single instruction can process 256 FP16 elements or 512 INT8 elements in parallel. Hardware Gather/Scatter support has been added, critical for MoE model sparse routing operations.

Scalar Unit (Control Unit): A RISC-style scalar processor handling loop control, address calculation, conditional branching, and exception handling. It runs a lightweight control thread coordinating the Cube and Vector units.

2.3.2 Key Improvements Over DaVinci 2.0

First, Mixed-Precision Tensor Core Upgrade. New dedicated FP8/MXFP8/HiF8/MXFP4 compute units support both E4M3 and E5M2 FP8 formats. A hardware dynamic scaling factor module automatically handles numerical scaling and overflow detection across different precisions, keeping accuracy loss within 0.5% for mixed-precision training—30% faster than software-based scaling.

Second, MoE-Specific Compute Pipeline. For trillion-parameter sparse MoE models, the Ascend 950 features a dedicated MoE acceleration unit that offloads expert gating, routing, and result reduction from the general compute cores. Expert dispatch latency drops from 12μs on the 910B to 4μs, improving MoE training throughput by 1.2×.

Third, Structured Sparse Acceleration. Built-in sparse compute units support 2:4 structured sparsity and 50% unstructured sparsity, doubling throughput in sparse mode. Unlike competitors that only support fixed sparsity patterns, the 950’s sparse unit supports dynamic sparse patterns.

Fourth, On-Chip SRAM Doubling. Each AI Core has 2MB of independent SRAM, totaling 256MB across the chip—double the 910B. On-chip bus bandwidth reaches 100 TB/s with only 1ns access latency. A dedicated KV cache buffer is allocated within the on-chip SRAM for attention computation.

2.3.3 Architecture Diagram

                    ┌─────────────────────────────────────┐
                    │    DaVinci 3.0 Architecture Overview  │
                    └─────────────────────────────────────┘
                                    │
         ┌──────────────────────────┼──────────────────────────┐
         │                          │                          │
         ▼                          ▼                          ▼
┌──────────────────┐    ┌──────────────────┐    ┌──────────────────┐
│   Cube Unit      │    │   Vector Unit    │    │   Scalar Unit    │
│   Matrix Compute │    │   Vector Engine   │    │   Control Core   │
│                  │    │                  │    │                  │
│ ┌────────────┐   │    │ SIMD: 512-bit   │    │ RISC Core        │
│ │16×16×16 3D │   │    │ FP16: 256/op    │    │ Branch Predict   │
│ │Systolic Arr│   │    │ INT8: 512/op    │    │ Address Calc     │
│ └────────────┘   │    │ HW Gather/Scatter│    │ Exception Handle │
│                  │    └──────────────────┘    └──────────────────┘
│ FP8: 1024/cycle  │            │                         │
│ MXFP4: 2048/cycle│            └──────────┬──────────────┘
└──────────────────┘                       │
         │                                 │
         └──────────────┬──────────────────┘
                        │
                        ▼
              ┌─────────────────────┐
              │   Unified Buffer    │
              │     8 MB SRAM       │
              │  100 TB/s on-chip BW│
              └─────────────────────┘
                        │
                        ▼
              ┌─────────────────────┐
              │   L2 Cache (32 MB)  │
              └─────────────────────┘
                        │
                        ▼
         ┌──────────────────────────────┐
         │  HBM3e / HiZQ 2.0 Main Mem   │
         │  96 GB (PR) / 144 GB (DT)     │
         │  4.6 TB/s (PR) / 4.0 TB/s(DT)│
         └──────────────────────────────┘
                        │
                        ▼
         ┌──────────────────────────────┐
         │   Lingqu 2.0 Interconnect    │
         │   8×256 GB/s SerDes          │
         │   2 TB/s total bandwidth     │
         └──────────────────────────────┘

3. Self-Developed Memory: HiZQ 2.0 vs HBM3e

3.1 Strategic Significance

One of the most notable innovations of the Ascend 950 series is Huawei’s self-developed high-bandwidth memory. This is not just a technical breakthrough but a strategic move for supply chain security.

The HBM (High Bandwidth Memory) market has long been dominated by Samsung, SK Hynix, and Micron—all Korean and American companies. US export controls on chips to China have further tightened the availability of high-end HBM. Huawei’s self-developed HiZQ 2.0 memory achieves autonomous control over the most critical memory component of AI chips.

HiZQ 2.0 (950DT):

• Capacity: 144 GB (2× HiZQ 1.0)
• Bandwidth: 4 TB/s (2.5× HiZQ 1.0)
• Technology: Self-developed TSV (Through Silicon Via) and hybrid bonding for higher density and lower power

HBM3e (950PR):

• Capacity: 96 GB
• Bandwidth: 4.6 TB/s
• Technology: Standard HBM3e interface for ecosystem compatibility

4. Lingqu 2.0 Interconnect: A Communication Revolution

4.1 Architecture Analysis

The Lingqu 2.0 interconnect uses a full optical switching architecture to solve the communication bottleneck at the physical layer.

Key specifications:

• 8 SerDes lanes per chip, each 256 GB/s unidirectional
• Total chip-to-chip interconnect bandwidth: 2 TB/s
• Single-hop latency: 200 ns
• Cluster end-to-end RTT: 3 μs
• Protocols: URMA, UB Memory, PCIe 5.0, UBoE

For comparison, traditional InfiniBand NDR 400 delivers 50 GB/s per lane with 600 ns single-hop latency. Lingqu 2.0 achieves 5× the bandwidth and 1/3 the latency.

4.2 Interconnect Topology Diagram

                    ┌────────────────────────────────────┐
                    │   Lingqu 2.0 Optical Interconnect   │
                    └────────────────────────────────────┘
                                  │
         ┌────────────────────────┼────────────────────────┐
         │                        │                        │
         ▼                        ▼                        ▼
   ┌──────────────┐      ┌──────────────┐        ┌──────────────┐
   │ 950DT Card 0 │      │ 950DT Card 1 │  ...   │ 950DT Card 63│
   │  ┌────┐ ┌────┐│      │  ┌────┐ ┌────┐│        │  ┌────┐ ┌────┐│
   │  │64  │ │64  ││      │  │64  │ │64  ││        │  │64  │ │64  ││
   │  │Core│ │Core││      │  │Core│ │Core││        │  │Core│ │Core││
   │  └────┘ └────┘│      │  └────┘ └────┘│        │  └────┘ └────┘│
   │  ┌──────────┐  │      │  ┌──────────┐  │        │  ┌──────────┐  │
   │  │Lingqu 2.0│  │      │  │Lingqu 2.0│  │        │  │Lingqu 2.0│  │
   │  │8×256GB/s │  │      │  │8×256GB/s │  │        │  │8×256GB/s │  │
   │  └────┬─────┘  │      │  └────┬─────┘  │        │  └────┬─────┘  │
   └───────┼────────┘      └───────┼────────┘        └───────┼────────┘
           │                      │                          │
           └──────────────────────┼──────────────────────────┘
                                  │
                        ┌─────────┴──────────┐
                        │   Optical Switch   │
                        │   Matrix 16×16     │
                        │   200 ns/hop       │
                        └────────────────────┘
                                  │
         ┌────────────────────────┼────────────────────────┐
         │                        │                        │
         ▼                        ▼                        ▼
   ┌──────────────┐      ┌──────────────┐        ┌──────────────┐
   │   Rack 0     │      │   Rack 1     │  ...   │   Rack 15    │
   │  64 Cards    │      │  64 Cards    │        │  64 Cards    │
   └──────────────┘      └──────────────┘        └──────────────┘
                                  │
                                  ▼
                    ┌──────────────────────────────┐
                    │ 1024-Card Standard Unit       │
                    │ 256 TB Unified Memory Space   │
                    │ 1 EFLOPS FP8 Total Compute    │
                    │ End-to-End RTT: 3 μs          │
                    └──────────────────────────────┘

4.3 Unified Memory Addressing

The most revolutionary innovation of the Ascend 950 SuperPoD is its native global unified memory architecture. In the standard 1024-card configuration, the Lingqu 2.0 protocol creates a 256 TB cross-physical-node unified memory address space. All accelerator cards can directly access memory data at any location within the cluster without explicit data copying.

To the software layer, the entire SuperPoD appears as a single device with 256 TB of unified memory. This fundamentally eliminates the “communication wall” problem in traditional distributed training, where communication wait time can account for over 65% of total training time.

5. Code: Ascend 950 Performance Simulator (Python)

#!/usr/bin/env python3
"""
ascend950_simulator.py
Huawei Ascend 950 Chip Performance Simulator
Simulates DaVinci 3.0 architecture compute scheduling, memory bandwidth, and communication latency
"""

import math
from dataclasses import dataclass
from typing import List, Dict
from enum import Enum


class Precision(Enum):
    FP32 = "fp32"
    FP16 = "fp16"
    BF16 = "bf16"
    FP8 = "fp8"
    MXFP8 = "mxfp8"
    HiF8 = "hif8"
    MXFP4 = "mxfp4"
    INT8 = "int8"


@dataclass
class Ascend950Spec:
    """Ascend 950 chip hardware specifications"""
    name: str
    transistor_count: int = 108_000_000_000
    process_node: str = "SMIC N+2 (5nm equivalent)"
    core_count: int = 64
    fp16_peak: float = 1.6  # PFLOPS
    fp8_peak: float = 1.0
    mxfp4_peak: float = 2.0
    memory_capacity: int = 96  # GB
    memory_bandwidth: float = 4.6  # TB/s
    interconnect_bw: float = 2.0  # TB/s
    l2_cache: int = 32  # MB
    sram_per_core: int = 2  # MB
    tdp: int = 600
    interconnect_latency_ns: int = 200
    rtt_latency_us: float = 3.0

    def compute_ops_per_second(self, precision: Precision) -> float:
        mapping = {
            Precision.FP32: self.fp16_peak * 0.125 * 1e15,
            Precision.FP16: self.fp16_peak * 1e15,
            Precision.BF16: self.fp16_peak * 1e15,
            Precision.FP8: self.fp8_peak * 1e15,
            Precision.MXFP8: self.fp8_peak * 1e15,
            Precision.HiF8: self.fp8_peak * 1e15,
            Precision.MXFP4: self.mxfp4_peak * 1e15,
            Precision.INT8: self.fp16_peak * 2e15,
        }
        return mapping[precision]

    def roofline_bound(self, arithmetic_intensity: float, precision: Precision) -> float:
        """Roofline model: returns performance ceiling for given arithmetic intensity"""
        peak_compute = self.compute_ops_per_second(precision)
        peak_bw = self.memory_bandwidth * 1e12
        compute_bound = peak_compute
        memory_bound = peak_bw * arithmetic_intensity
        return min(compute_bound, memory_bound)


def create_950pr() -> Ascend950Spec:
    return Ascend950Spec(
        name="Ascend 950PR", memory_capacity=96,
        memory_bandwidth=4.6, interconnect_bw=1.0,
    )


def create_950dt() -> Ascend950Spec:
    return Ascend950Spec(
        name="Ascend 950DT", memory_capacity=144,
        memory_bandwidth=4.0, interconnect_bw=2.0,
    )


@dataclass
class ModelConfig:
    name: str
    params_billions: int
    hidden_dim: int
    num_layers: int
    num_heads: int
    vocab_size: int
    seq_len: int
    moe_experts: int = 0
    moe_top_k: int = 0


LLAMA_70B = ModelConfig(
    "Llama-3 70B", 70, 8192, 80, 64, 128000, 8192)
LLAMA_405B = ModelConfig(
    "Llama-3 405B", 405, 16384, 126, 128, 128000, 8192)
MOE_2T = ModelConfig(
    "2T MoE", 2000, 24576, 96, 192, 256000, 16384,
    moe_experts=256, moe_top_k=8)


def estimate_model_memory(model: ModelConfig, precision: Precision) -> Dict[str, float]:
    """Estimate model memory footprint in GB"""
    bytes_per_param = {
        Precision.FP32: 4, Precision.FP16: 2, Precision.BF16: 2,
        Precision.FP8: 1, Precision.MXFP8: 1, Precision.HiF8: 1,
        Precision.INT8: 1, Precision.MXFP4: 0.5,
    }
    bpp = bytes_per_param[precision]
    params = model.params_billions * 1e9
    weight_mem = params * bpp / 1e9
    optimizer_mem = params * 4 * 2 / 1e9
    grad_mem = params * bpp / 1e9
    head_dim = model.hidden_dim // model.num_heads
    kv_per_token = 2 * model.num_layers * model.num_heads * head_dim * bpp / 1e9
    kv_cache_mem = kv_per_token * model.seq_len
    activation_mem = weight_mem * 0.2
    total = weight_mem + optimizer_mem + grad_mem + kv_cache_mem + activation_mem
    return {
        "weight": weight_mem, "optimizer": optimizer_mem,
        "gradient": grad_mem, "kv_cache": kv_cache_mem,
        "activation": activation_mem, "total": total,
    }


def simulate_training_throughput(
    chip: Ascend950Spec, model: ModelConfig,
    precision: Precision, num_chips: int,
) -> Dict:
    """Simulate large model training throughput"""
    model_mem = estimate_model_memory(model, precision)
    mem_per_gpu = model_mem["total"] / num_chips
    if mem_per_gpu > chip.memory_capacity:
        return {
            "feasible": False,
            "reason": f"OOM: need {mem_per_gpu:.1f}GB/GPU, have {chip.memory_capacity}GB",
        }
    params_per_step = model.params_billions * 1e9 / num_chips
    flops_per_step = 6 * params_per_step * model.seq_len
    bpp = {Precision.FP16: 2, Precision.FP8: 1, Precision.MXFP4: 0.5}[precision]
    comm_bytes = 2 * params_per_step * bpp
    comm_bw = chip.interconnect_bw * 1e12 * 0.8
    comm_time = comm_bytes / comm_bw
    compute_time = flops_per_step / chip.compute_ops_per_second(precision)
    step_time = compute_time + comm_time
    tokens_per_sec = model.seq_len * num_chips / step_time
    mfu = (flops_per_step * num_chips / step_time) / (
        chip.compute_ops_per_second(precision) * num_chips)
    return {
        "feasible": True, "model": model.name, "chip": chip.name,
        "num_chips": num_chips, "precision": precision.value,
        "tokens_per_sec": tokens_per_sec,
        "tokens_per_sec_per_gpu": tokens_per_sec / num_chips,
        "step_time_s": step_time, "mfu": mfu,
        "mem_per_gpu_gb": mem_per_gpu,
    }


def roofline_analysis(chip: Ascend950Spec):
    """Roofline model analysis"""
    print(f"\n===== Roofline Analysis: {chip.name} =====")
    print(f"{'Arith. Intensity (FLOPs/Byte)':<35} {'FP16 Perf (TFLOPS)':<25} {'Bound Type':<15}")
    print("-" * 75)
    for ai in [0.01, 0.1, 0.5, 1.0, 5.0, 10.0, 50.0, 100.0]:
        perf = chip.roofline_bound(ai, Precision.FP16)
        bound = "Memory" if perf < chip.compute_ops_per_second(Precision.FP16) else "Compute"
        print(f"{ai:<35.2f} {perf/1e12:<25.2f} {bound:<15}")
    print("-" * 75)


def main():
    print("=" * 80)
    print("Huawei Ascend 950 Performance Simulator")
    print("=" * 80)
    pr = create_950pr()
    dt = create_950dt()
    for chip in [pr, dt]:
        print(f"\n{chip.name}:")
        print(f"  Process: {chip.process_node}")
        print(f"  Transistors: {chip.transistor_count:,}")
        print(f"  FP16 Peak: {chip.fp16_peak} PFLOPS")
        print(f"  Memory: {chip.memory_capacity}GB @ {chip.memory_bandwidth}TB/s")
        print(f"  Interconnect: {chip.interconnect_bw} TB/s")
        print(f"  TDP: {chip.tdp}W")

    roofline_analysis(dt)

    print("\n===== Training Throughput Simulation =====")
    configs = [
        (LLAMA_70B, dt, Precision.FP16, 64),
        (LLAMA_70B, dt, Precision.FP8, 64),
        (LLAMA_405B, dt, Precision.FP8, 256),
        (LLAMA_405B, dt, Precision.MXFP4, 128),
        (MOE_2T, dt, Precision.FP8, 1024),
        (MOE_2T, dt, Precision.MXFP4, 512),
    ]
    header = f"{'Model':<20} {'Chip':<15} {'Chips':<8} {'Prec':<8} {'Tok/s':<12} {'Tok/s/GPU':<12} {'MFU':<8}"
    print(header)
    print("=" * len(header))
    for model, chip, prec, n in configs:
        r = simulate_training_throughput(chip, model, prec, n)
        if r.get("feasible"):
            print(f"{r['model']:<20} {r['chip']:<15} {r['num_chips']:<8} "
                  f"{r['precision']:<8} {r['tokens_per_sec']:<12.1f} "
                  f"{r['tokens_per_sec_per_gpu']:<12.1f} {r['mfu']:<8.2%}")
        else:
            print(f"{model.name:<20} {chip.name:<15} OOM: {r['reason']}")
    print("=" * len(header))

    print("\n===== Summary =====")
    print("Ascend 950DT FP16: 1.6 PFLOPS vs H200: 1.2 PFLOPS (+33%)")
    print("Lingqu 2.0 interconnect: 2 TB/s, 16x PCIe 5.0")
    print("Atlas 950 SuperPoD cluster utilization: 82-85%")


if __name__ == "__main__":
    main()

6. Code: All-Reduce Communication Benchmark (Go)

// allreduce_benchmark.go
// Distributed All-Reduce Communication Benchmark
// Compares Lingqu 2.0 optical interconnect vs traditional InfiniBand

package main

import (
	"fmt"
	"math"
	"time"
)

type InterconnectConfig struct {
	Name            string
	Bandwidth       float64 // GB/s
	SingleHopLat    float64 // ns
	SwitchLatency   float64 // ns
	ProtocolOverhead float64
}

var (
	Lingqu20 = InterconnectConfig{
		"Lingqu 2.0 Optical", 256, 200, 100, 0.02}
	InfiniBandNDR = InterconnectConfig{
		"InfiniBand NDR 400", 50, 600, 500, 0.08}
	PCIe50 = InterconnectConfig{
		"PCIe 5.0 x16", 31.5, 1000, 0, 0.05}
)

type AllReduceResult struct {
	Config       InterconnectConfig
	NumGPUs      int
	MessageSize  int
	TotalTime    time.Duration
	AlgoBandwidth float64
	BWEff        float64
}

func ringAllReduce(cfg InterconnectConfig, numGPUs int, msgSizeMB int) AllReduceResult {
	msgBytes := float64(msgSizeMB) * 1024 * 1024
	chunkSize := msgBytes / float64(numGPUs)
	effectiveBW := cfg.Bandwidth * 1024 * 1024 * 1024 * (1 - cfg.ProtocolOverhead)
	steps := numGPUs - 1
	transTime := chunkSize / effectiveBW
	latTime := float64(cfg.SingleHopLat) * 1e-9
	totalTimeSec := float64(steps) * 2 * (transTime + latTime)
	return AllReduceResult{
		Config: cfg, NumGPUs: numGPUs, MessageSize: msgSizeMB,
		TotalTime: time.Duration(totalTimeSec * 1e9),
		AlgoBandwidth: (msgBytes * 2) / totalTimeSec / 1e9,
		BWEff: 1.0 - float64(steps)*latTime/totalTimeSec,
	}
}

func hierarchicalAllReduce(cfg InterconnectConfig, numGPUs int, msgSizeMB int) AllReduceResult {
	msgBytes := float64(msgSizeMB) * 1024 * 1024
	effectiveBW := cfg.Bandwidth * 1024 * 1024 * 1024 * (1 - cfg.ProtocolOverhead)
	hops := int(math.Ceil(math.Log2(float64(numGPUs))))
	totalLat := float64(hops) * (cfg.SingleHopLat + cfg.SwitchLatency) * 1e-9
	transTime := msgBytes / (effectiveBW * float64(numGPUs))
	totalTimeSec := totalLat + transTime
	return AllReduceResult{
		Config: cfg, NumGPUs: numGPUs, MessageSize: msgSizeMB,
		TotalTime: time.Duration(totalTimeSec * 1e9),
		AlgoBandwidth: msgBytes / totalTimeSec / 1e9, BWEff: 1.0,
	}
}

func main() {
	fmt.Println("=" + repeat("=", 78) + "=")
	fmt.Println("  Distributed All-Reduce Benchmark")
	fmt.Println("  Lingqu 2.0 vs InfiniBand vs PCIe 5.0")
	fmt.Println("=" + repeat("=", 78) + "=")

	gpuConfigs := []int{8, 32, 128, 512, 1024}
	msgSizes := []int{1, 16, 64, 256, 1024}

	for _, msgSize := range msgSizes {
		fmt.Printf("\n--- Message Size: %d MB ---\n", msgSize)
		fmt.Printf("%-30s %-8s %-15s %-15s %-12s\n",
			"Interconnect", "GPUs", "Time", "BW (GB/s)", "Efficiency")
		fmt.Println(repeat("-", 85))

		for _, numGPUs := range gpuConfigs {
			lq := hierarchicalAllReduce(Lingqu20, numGPUs, msgSize)
			fmt.Printf("%-30s %-8d %-15v %-15.1f %-12.1f%%\n",
				"Lingqu 2.0 (HW Reduce)", numGPUs,
				lq.TotalTime, lq.AlgoBandwidth, lq.BWEff*100)

			ib := ringAllReduce(InfiniBandNDR, numGPUs, msgSize)
			fmt.Printf("%-30s %-8d %-15v %-15.1f %-12.1f%%\n",
				"InfiniBand NDR (Ring)", numGPUs,
				ib.TotalTime, ib.AlgoBandwidth, ib.BWEff*100)

			pcie := ringAllReduce(PCIe50, numGPUs, msgSize)
			fmt.Printf("%-30s %-8d %-15v %-15.1f %-12.1f%%\n",
				"PCIe 5.0 x16 (Ring)", numGPUs,
				pcie.TotalTime, pcie.AlgoBandwidth, pcie.BWEff*100)
			fmt.Println(repeat("-", 85))
		}
	}

	fmt.Println("\n" + "=" + repeat("=", 78) + "=")
	fmt.Println("  Key Findings")
	fmt.Println("=" + repeat("=", 78) + "=")
	fmt.Println()
	fmt.Println("1. Lingqu 2.0 single-hop latency (200ns) = 1/3 of IB (600ns)")
	fmt.Println("2. HW reduction via unified memory eliminates multi-step overhead")
	fmt.Println("3. At 1024 GPUs, Lingqu 2.0 is 5-10x faster than IB")
	fmt.Println("4. Lingqu 2.0 approaches 100% BW efficiency vs Ring algorithm degradation")
	fmt.Println("5. This enables 82-85% cluster utilization on Atlas 950 SuperPoD")
}

func repeat(s string, count int) string {
	r := ""
	for i := 0; i < count; i++ {
		r += s
	}
	return r
}

7. Code: Cluster Training Scheduler (Go)

// ascend_cluster_scheduler.go
// Atlas 950 SuperPoD Cluster Training Scheduler

package main

import (
	"fmt"
	"math"
	"sort"
	"sync"
	"time"
)

type Job struct {
	ID             string
	ModelName      string
	ParamB         int
	SeqLen         int
	NumGPUs        int
	Priority       int
	SubmittedAt    time.Time
}

type GPUNode struct {
	ID       int
	ChipType string
	MemoryGB int
	BW_TB    float64
	Status   string
	JobID    string
}

type SuperCluster struct {
	Name       string
	Nodes      []*GPUNode
	mu         sync.Mutex
	TotalNodes int
}

func NewSuperCluster(name string, chipType string, numNodes int) *SuperCluster {
	nodes := make([]*GPUNode, numNodes)
	memGB, bw := 144, 4.0
	if chipType == "950PR" {
		memGB, bw = 96, 4.6
	}
	for i := 0; i < numNodes; i++ {
		nodes[i] = &GPUNode{
			ID: i, ChipType: chipType,
			MemoryGB: memGB, BW_TB: bw, Status: "idle",
		}
	}
	return &SuperCluster{Name: name, Nodes: nodes, TotalNodes: numNodes}
}

func (sc *SuperCluster) ScheduleJob(job *Job) bool {
	sc.mu.Lock()
	defer sc.mu.Unlock()
	available := 0
	for _, node := range sc.Nodes {
		if node.Status == "idle" {
			available++
		}
	}
	if available < job.NumGPUs {
		return false
	}
	allocated := 0
	for _, node := range sc.Nodes {
		if node.Status == "idle" {
			node.Status = "busy"
			node.JobID = job.ID
			allocated++
			if allocated >= job.NumGPUs {
				break
			}
		}
	}
	return true
}

func (sc *SuperCluster) ReleaseJob(jobID string) {
	sc.mu.Lock()
	defer sc.mu.Unlock()
	for _, node := range sc.Nodes {
		if node.JobID == jobID {
			node.Status = "idle"
			node.JobID = ""
		}
	}
}

func (sc *SuperCluster) Utilization() float64 {
	sc.mu.Lock()
	defer sc.mu.Unlock()
	busy := 0
	for _, node := range sc.Nodes {
		if node.Status == "busy" {
			busy++
		}
	}
	return float64(busy) / float64(len(sc.Nodes))
}

func EstimateTrainingTime(job *Job, numNodes int) float64 {
	params := float64(job.ParamB) * 1e18
	chipFLOPS := 1.6e15
	totalFLOPs := 6 * params * float64(job.SeqLen) * 3.0
	commOverhead := 1.0 + 0.05*math.Log2(float64(numNodes))
	mfu := 0.75
	totalCompute := chipFLOPS * float64(numNodes) * mfu
	return totalFLOPs * commOverhead / totalCompute / 3600.0
}

type Scheduler struct {
	Cluster   *SuperCluster
	Queue     []*Job
	Running   map[string]*Job
	Completed []*Job
	mu        sync.Mutex
}

func NewScheduler(cluster *SuperCluster) *Scheduler {
	return &Scheduler{
		Cluster: cluster, Queue: make([]*Job, 0),
		Running: make(map[string]*Job),
	}
}

func (s *Scheduler) AddJob(job *Job) {
	s.mu.Lock()
	defer s.mu.Unlock()
	job.SubmittedAt = time.Now()
	s.Queue = append(s.Queue, job)
}

func (s *Scheduler) Schedule() {
	s.mu.Lock()
	defer s.mu.Unlock()
	sort.Slice(s.Queue, func(i, j int) bool {
		return s.Queue[i].Priority > s.Queue[j].Priority
	})
	var remaining []*Job
	for _, job := range s.Queue {
		if s.Cluster.ScheduleJob(job) {
			s.Running[job.ID] = job
			hours := EstimateTrainingTime(job, job.NumGPUs)
			fmt.Printf("  [Scheduled] %s (%s, %d GPUs, Pri=%d) ~%.1f hrs\n",
				job.ID, job.ModelName, job.NumGPUs, job.Priority, hours)
		} else {
			remaining = append(remaining, job)
		}
	}
	s.Queue = remaining
}

func (s *Scheduler) PrintStatus() {
	s.mu.Lock()
	defer s.mu.Unlock()
	fmt.Printf("\nCluster: %s\n", s.Cluster.Name)
	fmt.Printf("Total Nodes: %d, Utilization: %.1f%%\n",
		s.Cluster.TotalNodes, s.Cluster.Utilization()*100)
	fmt.Printf("Running: %d, Queued: %d, Completed: %d\n",
		len(s.Running), len(s.Queue), len(s.Completed))
	idle, busy := 0, 0
	for _, n := range s.Cluster.Nodes {
		if n.Status == "idle" {
			idle++
		} else {
			busy++
		}
	}
	fmt.Printf("Idle=%d Busy=%d\n", idle, busy)
}

func main() {
	fmt.Println("=" + repeat("=", 78) + "=")
	fmt.Println("  Atlas 950 SuperPoD Cluster Training Scheduler")
	fmt.Println("=" + repeat("=", 78) + "=")

	cluster := NewSuperCluster("Atlas 950 SuperPoD", "950DT", 1024)
	scheduler := NewScheduler(cluster)

	jobs := []*Job{
		{"J001", "Llama-3 70B", 70, 8192, 64, 3, time.Time{}},
		{"J002", "Llama-3 405B", 405, 8192, 256, 5, time.Time{}},
		{"J003", "Qwen 3 72B", 72, 32768, 128, 2, time.Time{}},
		{"J004", "DeepSeek MoE 1T", 1000, 16384, 512, 4, time.Time{}},
		{"J005", "PanGu 200B", 200, 8192, 128, 3, time.Time{}},
		{"J006", "MoE 2T", 2000, 16384, 1024, 5, time.Time{}},
	}

	fmt.Println("\nSubmitted Jobs:")
	for _, job := range jobs {
		hours := EstimateTrainingTime(job, job.NumGPUs)
		fmt.Printf("  %s: %s (%dB, %d GPUs, Pri=%d) ~%.1f hrs\n",
			job.ID, job.ModelName, job.ParamB, job.NumGPUs, job.Priority, hours)
		scheduler.AddJob(job)
	}

	fmt.Println("\n--- Round 1 Scheduling ---")
	scheduler.Schedule()
	scheduler.PrintStatus()

	fmt.Println("\n--- Simulating Job Completion ---")
	for _, id := range []string{"J001", "J003"} {
		if job, ok := scheduler.Running[id]; ok {
			scheduler.Cluster.ReleaseJob(id)
			delete(scheduler.Running, id)
			scheduler.Completed = append(scheduler.Completed, job)
			fmt.Printf("  %s completed\n", id)
		}
	}

	fmt.Println("\n--- Round 2 Scheduling (after resources freed) ---")
	scheduler.Schedule()
	scheduler.PrintStatus()
}

func repeat(s string, count int) string {
	r := ""
	for i := 0; i < count; i++ {
		r += s
	}
	return r
}

8. Ecosystem and Industry Impact

8.1 Cloud Provider Adoption

Major Chinese cloud providers have rapidly adopted the Ascend 950 series. Alibaba Cloud has launched Ascend 950 instances offering elastic training and inference services. Tencent Cloud has completed Ascend 950 adaptation for Hunyuan model training. Baidu AI Cloud’s Qianfan platform natively supports Ascend 950 with ERNIE model optimization. These adoptions signal a fundamental shift in China’s AI infrastructure landscape, moving from a predominantly NVIDIA-based ecosystem to one that increasingly relies on domestic alternatives.

8.2 Domestic LLM Ecosystem

Adaptation progress with domestic large language models has been remarkably swift. DeepSeek has completed full optimization for the Ascend 950DT, reporting significant performance gains in MoE training workloads. Moonshot AI announced that its Kimi K3 model running on Ascend 950DT outperforms the same model on NVIDIA B300 hardware in specific inference benchmarks. The Qwen team at Alibaba has validated trillion-parameter model training on the Ascend 950 cluster, demonstrating the platform’s capability to handle the most demanding large-scale training workloads.

This ecosystem adaptation is not accidental. Huawei has invested heavily in the CANN (Compute Architecture for Neural Networks) software stack, which now supports over 95% of mainstream large model operators. The CANN 8.0 release, specifically optimized for the 950DT, includes 1,200+ operators covering Transformer, MoE, and attention computation scenarios. Average operator performance is 40% higher than the previous generation 910B. The CANN open-source community has grown to over 3,500 monthly active developers, with 67 community projects and 12.44 million lines of open-source code.

8.3 AEI Report Analysis

The American Enterprise Institute (AEI) report published on August 5, 2026, represents a significant acknowledgment from a US-based think tank. The report’s core conclusions are noteworthy:

First, Huawei could produce approximately 3.3 million Ascend series accelerators by 2028. This production volume, if achieved, would represent a dramatic scaling of domestic AI chip manufacturing capacity. For context, this would be roughly equivalent to the entire global AI accelerator market size in 2023.

Second, these chips could meet one-third to one-half of China’s AI compute demand by 2028. This is a remarkably high self-sufficiency ratio, considering that in 2022, China’s AI chip market was over 95% dependent on NVIDIA imports.

Third, the Ascend 950 series annual production target of approximately 800,000 units suggests that Huawei is confident about its manufacturing ramp. The 950DT going live four months ahead of schedule is a positive signal for yield improvement at SMIC’s N+2 process.

The AEI report’s publication is itself significant. It represents a departure from the typically pessimistic US establishment view of Chinese semiconductor capabilities. The acknowledgment that Huawei could meet half of China’s AI compute demand within two years suggests that US policy makers are recalibrating their assessment of Chinese technological capabilities.

8.4 Yield Challenges and Manufacturing Reality

While the Ascend 950 series achieves impressive technical specifications, the reality of manufacturing at SMIC’s N+2 process presents formidable challenges. Unlike TSMC’s 4nm or 5nm processes that use EUV lithography, SMIC relies on deep ultraviolet (DUV) lithography with multiple patterning. This technique requires more mask layers, introduces higher defect risks, and results in slower yield ramp.

Industry estimates suggest that SMIC’s N+2 process initially achieves yields of 30-40% for large dies like the Ascend 950 with its 108 billion transistors on a massive die. This is significantly lower than TSMC’s mature 5nm yields of 80-90% for similar-sized chips. Huawei and SMIC have been working on design-technology co-optimization (DTCO) to improve yields, including redundant circuit design that adds spare compute units that can be laser-repaired if primary units fail, adaptive voltage scaling that compensates for process variation by adjusting operating voltages per chip, and yield-aware floorplanning that places critical high-speed circuits in areas with lower defect density.

The HBM (High Bandwidth Memory) supply is another critical bottleneck. While Huawei’s self-developed HiZQ 2.0 memory reduces dependence on Samsung and SK Hynix, the TSV (Through Silicon Via) packaging and hybrid bonding processes also require yield ramp time. Industry projections suggest that Ascend 950PR production could reach approximately 800,000 units in 2026, with 950DT volumes dependent on HiZQ 2.0 capacity release.

8.5 The Geopolitical Chess Match

The Ascend 950 series was born in the crucible of US export controls. Since October 2022, when the US first imposed AI chip export controls banning NVIDIA A100 and H100 sales to China, the restrictions have expanded repeatedly. Huawei was forced to shift from TSMC to SMIC for fabrication, develop self-designed HBM to replace Samsung and SK Hynix imports, create its own interconnect protocol (Lingqu 2.0) to avoid restrictions on NVLink-like technologies, and build a complete software stack (CANN 8.0) from scratch to replace CUDA.

However, the effectiveness of export controls is diminishing. The AEI report acknowledges that Huawei could meet one-third to one-half of China’s AI compute demand by 2028. This means that while US export controls have slowed China’s AI chip development, they have not prevented China from achieving self-sufficiency in AI compute.

Paradoxically, the restrictions have accelerated China’s indigenous innovation. The “restricted” NVIDIA H20 chip, specially designed for the Chinese market, delivers only 15-20% of the performance of the original H100 while still carrying a premium price due to channel costs and scarcity. Meanwhile, the Ascend 950 series has already surpassed the H200 in FP16 compute and cluster efficiency. The strategy of “controlling through restriction” is proving increasingly ineffective—restrictions have instead accelerated China’s autonomous development.

8.6 International Market Expansion

The Ascend 950 series is not limited to the Chinese domestic market. According to public information, Korean cloud providers have already secured initial orders, and Malaysia plans to deploy 3,000 Ascend servers. Southeast Asia and Latin America are becoming key regions for Ascend 950 series international expansion.

At WAIC 2026, Huawei announced that the Lingqu 2.0 protocol is fully open to third-party hardware manufacturers. More than ten domestic hardware manufacturers have completed protocol adaptation, covering optical modules, switches, and server systems across the industry chain. This open ecosystem strategy helps reduce migration costs for international customers and accelerates the globalization of the Ascend ecosystem.

8.7 Memory Bandwidth Benchmark Analysis

To understand the practical impact of the Ascend 950’s memory bandwidth advantage, we need to examine the memory access patterns of large language model inference. The Decode phase of LLM inference is particularly memory-intensive because each generated token requires reading the entire KV cache from HBM. For a 70B parameter model with 80 Transformer layers, 64 attention heads, and a sequence length of 8192, the KV cache alone occupies approximately 30-40 GB. Each token generation step reads this entire cache, creating a massive memory bandwidth demand.

The Ascend 950DT’s 4.0 TB/s memory bandwidth translates to a theoretical maximum of 4,000 GB of data read per second. At 200 tokens per second generation rate, each token has 20 GB/s of bandwidth available. For a 70B model with a 35 GB KV cache, this means the cache can be read in approximately 8.75 milliseconds, well within the latency budget for interactive applications.

In contrast, the H200’s 3.35 TB/s bandwidth would require approximately 10.4 milliseconds for the same KV cache read. While this difference seems small, it compounds significantly under high concurrency. When serving 1024 concurrent requests, the total bandwidth demand scales linearly, and the 950DT’s 19% bandwidth advantage becomes a critical differentiator.

8.8 The DaVinci 3.0 Cube Unit in Detail

The 3D Cube is the most distinctive feature of the DaVinci architecture. Unlike traditional GPU tensor cores that operate on 2D matrix tiles, the DaVinci Cube operates on 3D volumes (16×16×16), enabling more efficient execution of batched matrix multiplications commonly found in transformer attention mechanisms.

The Cube unit processes 16×16×16 sub-blocks: it loads a 16×16 slice of matrix A and a 16×16 slice of matrix B, multiplies them, and accumulates the result into a 16×16 output tile. All 4,096 multiply-accumulate operations execute in parallel within a single instruction cycle.

The key innovation in DaVinci 3.0 is the addition of FP8 and MXFP4 data paths alongside the existing FP16 and BF16 paths. The FP8 path supports both E4M3 (4 exponent bits, 3 mantissa bits, higher precision for weights and activations) and E5M2 (5 exponent bits, 2 mantissa bits, wider dynamic range for gradients) formats. The hardware automatically selects the appropriate format based on the operation type, with no software intervention required.

8.9 Precision Formats and Quantization Strategy

The Ascend 950 supports an extensive range of precision formats. FP32 delivers 0.2 PFLOPS for initial model training where maximum precision is required. FP16 and BF16 are the standard workhorses delivering 1.6 PFLOPS each, with BF16 preferred for training due to its wider dynamic range. FP8 (E4M3 and E5M2) delivers 1.0 PFLOPS with hardware dynamic scaling that maintains accuracy within 0.5% of FP16. MXFP8 provides enhanced accuracy with per-tile scaling factors. HiF8 (Huawei Intelligent FP8) uses adaptive precision allocation based on tensor value distributions. MXFP4 delivers 2.0 PFLOPS for aggressively quantized models, enabling 4× the inference throughput of FP16 when combined with the 950DT’s memory bandwidth.

The recommended quantization strategy follows a progressive approach: start with FP16/BF16 training for baseline accuracy, apply FP8 quantization-aware training for the first optimization pass, use post-training quantization to FP8 or MXFP8 for inference, and experiment with MXFP4 for maximum throughput.

8.10 The CANN 8.0 Software Stack

CANN 8.0 is the software stack that bridges the hardware capabilities of the Ascend 950 with developer-facing frameworks. Key components include the Ascend C Programming Framework for writing high-performance operators, the ACL (Ascend Compute Library) with 1,200+ pre-optimized operators achieving 85% of theoretical peak performance, the FE (Fusion Engine) that automatically combines operators for up to 3× performance improvement, the AOE (Ascend Optimization Engine) for automatic tuning, and framework adapters for PyTorch, MindSpore, and PaddlePaddle.

8.11 Full Comparison with NVIDIA H200

The comparison between the Ascend 950DT and NVIDIA H200 is the most discussed topic in the industry. Based on publicly available specifications, the Ascend 950DT surpasses the H200 in multiple dimensions.

FP16 Compute: The 950DT achieves 1.6 PFLOPS versus the H200’s 1.2 PFLOPS, a 33% advantage enabled by the DaVinci 3.0 architecture’s 3D Cube design and higher compute density.

Memory Bandwidth: The 950DT’s 4.0 TB/s (HiZQ 2.0) and 950PR’s 4.6 TB/s (HBM3e) both significantly exceed the H200’s 3.35 TB/s. Higher memory bandwidth translates directly to better performance in memory-intensive tasks like LLM Decode inference.

Interconnect Bandwidth: The 950DT’s 2 TB/s Lingqu 2.0 far exceeds the H200’s 900 GB/s NVLink. In thousand-card cluster training, interconnect bandwidth directly determines communication efficiency.

Cluster Efficiency: The Ascend 950 SuperPoD achieves 82-85% effective compute utilization through unified memory addressing, while the NVIDIA GB300 cluster typically achieves around 65% utilization. This means that even with equivalent single-card compute, the Ascend 950 cluster delivers approximately 30% more effective compute at the 1024-card scale.

Cost-Effectiveness: A 1024-card Ascend 950 SuperPoD has a total hardware cost of approximately 150 million RMB (about $21 million), with a unit FP8 compute cost of approximately 15 RMB/TFLOPS. For equivalent effective compute, the NVIDIA solution, accounting for export control premiums, costs approximately 1.5-2× more.

9. The Road Ahead: Ascend 960 and Beyond

While the Ascend 950 series represents a significant achievement, Huawei has already outlined an ambitious roadmap for future generations. The Ascend 960 (targeting Q4 2027) aims for 3.2 PFLOPS FP16 (double the 950), 256 GB HBM4 memory, 8 TB/s memory bandwidth, and 4 TB/s interconnect. The Atlas 960 SuperPoD will scale to 15,488 cards, delivering 30 EFLOPS FP8. The Ascend 970 (targeting Q4 2028) targets 6.4 PFLOPS FP16, 512 GB memory, 16 TB/s bandwidth, and 8 TB/s interconnect. The Atlas 970 SuperCluster is planned to exceed 1 million NPUs, delivering over 2 ZFLOPS FP8 compute.

These projections suggest that Huawei is maintaining a “one generation per year, compute doubling each generation” cadence. If successful, the Ascend 970 would deliver system-level performance comparable to the most powerful supercomputers in the world.

However, significant challenges remain. The transition to SMIC’s next-generation process will be critical for achieving the 970’s power density and compute targets. The development of HBM4-class memory, requiring even more advanced TSV and bonding technology, will also be a key technical hurdle.

Nevertheless, the Ascend 950 series has demonstrated that system-level innovation can compensate for process technology disadvantages. The unified memory architecture, optical interconnect, and specialized compute units of the 950 have proven that there are multiple paths to AI compute leadership beyond simply shrinking transistors.

8.12 The Memory Hierarchy and Data Flow

Understanding the memory hierarchy of the Ascend 950 is essential for optimizing operator performance. The hierarchy consists of four levels. Level 1 is the Register File within each AI Core, providing sub-nanosecond access latency. Level 2 is the Local Memory or Unified Buffer, an 8 MB workspace per AI Core that is double-buffered. Level 3 is the 32 MB L2 Cache shared across all AI Cores. Level 4 is the main HBM3e or HiZQ 2.0 memory.

The data flow for a typical matrix multiplication follows this path: input matrices are fetched from HBM to L2 Cache, then transferred to the Unified Buffer in 16x16 tiles. The Cube unit reads tiles from the UB, performs matrix multiplication, and writes results back. This pipeline is orchestrated by the CANN 8.0 runtime, which schedules data movement and computation to maximize overlap. The double-buffering mechanism ensures that while one buffer is consumed by the Cube, the next batch of data is loaded into the other buffer, achieving near 100 percent compute utilization for well-structured operators.

10. Developer Recommendations

For engineers developing on the Ascend platform, the following recommendations can help maximize performance. First, leverage the CANN 8.0 ecosystem with its 1,200+ optimized operators delivering 40% average performance improvement over the 910B. Second, adopt P/D separation architecture for inference deployment, using 950PR for compute-intensive Prefill and 950DT for memory-intensive Decode to achieve optimal cost-performance ratio. Third, utilize unified memory addressing in distributed training to simplify data and model parallelism implementations. Fourth, monitor the Lingqu open ecosystem for third-party compatible products that can reduce supply chain risks.

11. Conclusion

The Ascend 950 series marks a new phase in China’s AI chip industry. From single-card performance to cluster efficiency, from chip design to software ecosystem, from manufacturing process to memory technology, the Ascend 950 achieves a comprehensive generational leap. The DaVinci 3.0’s MoE-specific acceleration, Lingqu 2.0’s optical interconnect, and unified memory addressing represent industry-leading innovations that enable the 950 to surpass the NVIDIA H200 in multiple performance dimensions.

More importantly, this technology roadmap is fully autonomous, from chip design to fabrication, from memory technology to interconnect protocols, from operator libraries to training frameworks. This is not just a demonstration of technical capability but a guarantee of supply chain security and national strategic autonomy. From follower to competitor and, in select areas, leader, the Huawei Ascend 950 series is writing a new chapter in the history of Chinese AI chips. This is not the finish line, but the starting point of a new era. For developers, researchers, and industry observers, the Ascend 950 represents a watershed moment that demands attention and careful study. The technological trajectory it establishes will shape the global AI compute landscape for years to come, forcing a re-evaluation of assumptions about谁的 leadership in artificial intelligence hardware. The competition between Huawei and NVIDIA in the AI chip space is now the defining technology rivalry of the decade, and the Ascend 950 series has made it clear that this race is far from decided.

All technical parameters in this article are sourced from Huawei’s official public disclosures, WAIC 2026 technical forums, AEI reports, and public media coverage. Code examples are provided for educational and research purposes only.

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