Deep Dive into Cerebras CS-4: Three WSE-3T Wafers, 30x Faster Inference Than GPU
1. Introduction: AI Inference Enters the Microsecond Era
On August 18, 2026, at the SUPERNOVA event in San Francisco, Cerebras Systems dropped a bombshell: the CS-4 rack-scale AI system. This wasn’t just another hardware iteration — it was a fundamental challenge to the GPU-dominated AI infrastructure landscape.
Three WSE-3T (Wafer Scale Engine 3 Turbo) processors packed into a single rack, delivering 750 PFLOPS of sparse FP16 compute, 129.6 PB/s of memory bandwidth, and 7.2 Tbps of I/O throughput. But the headline number that made the industry sit up was 4,400+ tokens per second per user on GPT-OSS-120B — up to 30x faster than GPU-based solutions.
Andrew Feldman, Cerebras CEO, captured the moment with a simple statement: “In AI, speed is productivity.” Behind that statement lies a harsh reality: for a decade, GPUs have dominated AI acceleration by default, not by design. Their architecture was built for graphics rendering, retrofitted for AI. Wafer-scale computing — once dismissed as impossible — is now proving its case with the hardest possible evidence.
This article breaks down the CS-4 across five dimensions: processor architecture, system design, inference performance, real-world code, and industry impact.
2. WSE-3T: Not New Silicon, But Twice the Performance
2.1 The “Crazy” Idea Behind Wafer-Scale Computing
To understand the WSE-3T, you first need to understand why Cerebras chose the wafer-scale path in the first place.
Traditional GPU systems take a silicon wafer, cut it into individual dies, package them, and mount them on a PCB with HBM memory stacked alongside. The communication between compute and memory goes through an interposer, adding latency measured in microseconds. NVIDIA’s H100/B200 requires 8 GPUs linked via NVLink to form a single node, with significant communication overhead.
Cerebras took the opposite approach: don’t cut the wafer. Use the entire thing as one chip.
┌─────────────────────────────────────────────────────────────┐
│ WSE-3T Wafer Floorplan │
│ │
│ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ │
│ │Core │ │Core │ │Core │ │Core │ │Core │ │Core │ │
│ │00001│ │00002│ │00003│ │ ... │ │ ... │ │89999│ │
│ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ │
│ │ │ │ │ │ │ │
│ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ │
│ │SRAM │ │SRAM │ │SRAM │ │SRAM │ │SRAM │ │SRAM │ │
│ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ │
│ │ │ │ │ │ │ │
│ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐ │
│ │Core │ │Core │ │Core │ │Core │ │Core │ │Core │ │
│ │90001│ │90002│ │90003│ │ ... │ │ ... │ │179999│ │
│ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ │
│ │ │ │ │ │ │ │
│ ┌──┴──────────┴──────────┴──────────┴──────────┴──┐ │
│ │ 2D Mesh Fabric (53.5 PB/s) │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ 4 Trillion Transistors | 900K AI Cores | 46,225mm² | 44GB SRAM│
└─────────────────────────────────────────────────────────────┘
Figure 1: WSE-3T Wafer Floorplan — 900,000 AI cores connected via 2D mesh, each with dedicated SRAM
2.2 WSE-3T: The Overclock That Changed Everything
Here’s the most surprising fact about the WSE-3T: the silicon is identical to the WSE-3. Same TSMC 5nm process, same 4 trillion transistors, same 900,000 AI cores, same 46,225mm² area, same 44GB on-chip SRAM.
So where does the 2x performance come from? The answer is deceptively simple and brutally hard: frequency doubled from 1.4GHz to 2.8GHz.
This sounds like “overclocking” in the consumer PC sense, but the engineering challenge is orders of magnitude harder. The WSE-3T is a single piece of silicon 60x larger than a typical GPU die. Distributing a global clock across that area at 2.8GHz while managing power delivery and thermal dissipation at kilowatt scales is a system-level nightmare. The solution wasn’t in the chip — it was in the power delivery and cooling architecture (the “backpack” design we’ll cover in section 3).
# WSE-3 vs WSE-3T Performance Comparison
wse3 = {
"transistors": 4e12,
"cores": 900_000,
"frequency_ghz": 1.4,
"sparse_fp16_pflops": 125,
"memory_bw_pbs": 21.6,
"fabric_bw_pbs": 26.75,
"io_bw_tbps": 1.2,
"sram_gb": 44
}
wse3t = {
"transistors": 4e12,
"cores": 900_000,
"frequency_ghz": 2.8,
"sparse_fp16_pflops": 250,
"memory_bw_pbs": 43.2,
"fabric_bw_pbs": 53.5,
"io_bw_tbps": 2.4,
"sram_gb": 44
}
print(f"{'Metric':<25} {'WSE-3':<15} {'WSE-3T':<15} {'Ratio':<10}")
print("-" * 65)
for key, v3 in wse3.items():
v3t = wse3t[key]
ratio = v3t / v3 if v3 != 0 else 0
print(f"{key:<25} {str(v3):<15} {str(v3t):<15} {ratio:<10.1f}x")
The key insight: every bandwidth metric doubled exactly. This is a direct consequence of the frequency doubling. In a wafer-scale architecture, memory bandwidth, on-chip fabric bandwidth, and I/O bandwidth all scale linearly with frequency. Cerebras doesn’t need HBM4 or CoWoS-L to get a bandwidth boost — they just turn up the clock.
2.3 SRAM vs DRAM: The Wafer-Scale “Nuclear Weapon”
Traditional GPU systems rely on HBM (High Bandwidth Memory), which is fundamentally DRAM. DRAM offers high density and low cost, but suffers from high latency (50-100ns) and bandwidth constraints dictated by the HBM interface standard.
Cerebras takes a completely different approach: 44GB of SRAM integrated directly on the wafer. SRAM is 10-100x faster than DRAM, with latency measured in nanoseconds.
┌─────────────────────────────────────────────────────────────────┐
│ SRAM vs DRAM Comparison │
├──────────────────┬──────────────────┬────────────────────────────┤
│ Dimension │ SRAM (CS-4) │ DRAM HBM3e (GPU) │
├──────────────────┼──────────────────┼────────────────────────────┤
│ Access Latency │ ~1-3 ns │ ~50-100 ns │
│ Bandwidth Density│ Extreme (on-die) │ Limited by HBM pins │
│ Capacity │ 44GB (on-wafer) │ 80-192GB (stacked) │
│ Power Efficiency │ Very High │ Moderate (needs PHY) │
│ Process Cost │ High (area cost) │ Low (separate die) │
│ BW Scalability │ Linear w/ freq │ Needs new HBM standard │
│ Per-OP Energy │ ~5 pJ │ ~20-30 pJ (via HBM PHY) │
└──────────────────┴──────────────────┴────────────────────────────┘
Figure 2: SRAM vs DRAM — SRAM offers overwhelming advantages in latency and bandwidth density
For inference workloads, memory bandwidth is the bottleneck, not compute. The speed at which model parameters can be moved from memory to compute units directly determines token generation speed. SRAM’s bandwidth advantage makes the WSE-3T a natural fit for inference — and the gap widens as model sizes grow.
3. CS-4 System Architecture: The Nexus Platform Revolution
3.1 Modular Design: Compute/Power/I/O Separation
The CS-4 is far more than three WSE-3T chips stacked in a rack. It’s the first product built on Cerebras Nexus Platform Architecture — a design that will span CS-4, CS-5, and CS-6 generations.
The core idea: functional separation of compute, power, and I/O.
┌───────────────────────────────────────────────────────────────┐
│ CS-4 Nexus Rack Architecture │
│ (Front View) │
├───────────────────────────────────────────────────────────────┤
│ ┌──────────────────────────────────────────────────────────┐│
│ │ Power Shelf ││
│ │ ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ ││
│ │ │ PSU #1 │ │ PSU #2 │ │ PSU #3 │ │ PSU #4 │ ││
│ │ └────────┘ └────────┘ └────────┘ └────────┘ ││
│ └──────────────────────────────────────────────────────────┘│
│ │
│ ┌──────────────────────────────────────────────────────────┐│
│ │ Cooling Module ││
│ │ ┌──────────────────────────────────────────────────┐ ││
│ │ │ Direct Liquid Cooling Loop │ ││
│ │ └──────────────────────────────────────────────────┘ ││
│ └──────────────────────────────────────────────────────────┘│
│ │
│ ┌──────┐ ┌────────────┐ ┌──────┐ ┌────────────┐ ┌──────┐│
│ │ I/O │ │ WSE-3T │ │ I/O │ │ WSE-3T │ │ I/O ││
│ │Module│ │ Backpack #1│ │Module│ │ Backpack #2│ │Module││
│ └──────┘ └────────────┘ └──────┘ └────────────┘ └──────┘│
│ │
│ ┌────────────┐ │
│ │ WSE-3T │ │
│ │ Backpack #3│ │
│ └────────────┘ │
│ │
│ ┌──────────────────────────────────────────────────────────┐│
│ │ Network Module ││
│ │ RoCE v2 RDMA | Direct Wafer Links | 7.2 Tbps ││
│ └──────────────────────────────────────────────────────────┘│
└───────────────────────────────────────────────────────────────┘
Figure 3: CS-4 Nexus Rack Architecture — Compute, power, and I/O as physically separate, independently upgradeable modules
3.2 The “Backpack” Design: A Power Delivery Masterpiece
The most impressive engineering innovation in the CS-4 is the Wafer-Scale Backpack. This design moves the voltage regulator module (VRM) from 50mm away (typical GPU layout) to just 0.5mm from the processor — a 100x reduction in physical distance.
┌─────────────────────────────────────────────────────────────────────┐
│ Wafer-Scale Backpack Design │
│ │
│ Traditional GPU Approach: │
│ ┌──────────┐ 50mm ┌──────────────┐ │
│ │ VRM │ ────────────────────────── │ GPU Die │ │
│ │ (PCB) │ Board-level losses │ (on PCB) │ │
│ └──────────┘ └──────────────┘ │
│ │
│ CS-4 "Backpack" Approach: │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ ┌──────────────┐ 0.5mm ┌──────────────────────┐ │ │
│ │ │ Power Conv │ ────────── │ WSE-3T Wafer │ │ │
│ │ │ (VRM) │ Integrated │ + Liquid Cooling │ │ │
│ │ │ │ Package │ + I/O + Control │ │ │
│ │ └──────────────┘ └──────────────────────┘ │ │
│ │ <─────────── Wafer-Scale Backpack (3D integrated) ────>│ │
│ └──────────────────────────────────────────────────────────┘ │
│ │
│ Result: Board-level power losses nearly eliminated │
│ → 2x more power delivered to WSE-3T within same power budget │
│ → Frequency 1.4GHz → 2.8GHz enabled │
└─────────────────────────────────────────────────────────────────────┘
Figure 4: CS-4 “Backpack” Power Delivery — 100x closer VRM, nearly eliminating board-level power loss
The value of this design extends far beyond “overclocking.” In traditional GPU designs, current travels from the VRM through PCB traces to the chip. Every inch of PCB trace introduces IR drop and resistive power loss. When a processor consumes kilowatts, these losses are significant. Cerebras’s solution attaches the power conversion directly to the back of the wafer, using the shortest possible electrical path. This is a paradigm-level innovation in power delivery architecture.
3.3 Switch-Free Direct Topology: The Secret Behind 2μs Latency
For multi-wafer interconnects, Cerebras made a remarkably bold decision: eliminate the switch chips entirely.
┌─────────────────────────────────────────────────────────────────────────┐
│ Traditional GPU vs CS-4 Switch-Free Topology │
├─────────────────────────────────────────────────────────────────────────┤
│ │
│ Traditional GPU Multi-Node (8×H100): │
│ │
│ ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ │
│ │GPU 0│──┐ │GPU 1│──┐ │GPU 2│──┐ │GPU 3│ │
│ └──┬──┘ │ └──┬──┘ │ └──┬──┘ │ └──┬──┘ │
│ │ │ │ │ │ │ │ │ │
│ ┌──┴─────┴──┐ ┌─┴─────┴──┐ ┌─┴─────┴──┐ ┌─┴─────┴──┐ │
│ │ NVSwitch │ │ NVSwitch │ │ NVSwitch │ │ NVSwitch │ │
│ │ (5μs) │ │ (5μs) │ │ (5μs) │ │ (5μs) │ │
│ └───────────┘ └──────────┘ └───────────┘ └───────────┘ │
│ │
│ CS-4 Three-Wafer Direct Connect: │
│ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ ┌───────────┐ Direct Wafer Link ┌───────────┐ │ │
│ │ │ WSE-3T │◄═══════════════════════►│ WSE-3T │ │ │
│ │ │ Backpack │ (No switch, 2μs) │ Backpack │ │ │
│ │ └─────┬─────┘ └─────┬─────┘ │ │
│ │ │◄═══════════════════════════════════════►│ │ │
│ │ ┌─────┴─────┐ │ │ │
│ │ │ WSE-3T │ │ │ │
│ │ │ Backpack │ │ │ │
│ │ └───────────┘ │ │ │
│ └──────────────────────────────────────────────────────────┘ │
│ │
│ Latency: 5μs (NVSwitch) → 2μs (Direct Wafer Links) │
│ Components: 50% fewer components vs CS-3 │
└─────────────────────────────────────────────────────────────────────────┘
Figure 5: Switch-Free Topology vs Traditional GPU Multi-Chip — CS-4 removes switches, cuts latency from 5μs to 2μs
Three WSE-3T processors are connected via Direct Wafer Links, forming a tightly coupled compute cluster with inter-wafer latency as low as 2 microseconds. This allows them to function as a single “super-chip,” supporting models with over 50 trillion parameters.
4. Inference Performance: The Engineering Behind 30x
4.1 Disaggregated Inference Pipeline
The CS-4 supports disaggregated inference, arguably its most important architectural innovation.
Inference has two phases:
- Prefill: Process the input prompt, compute KV cache. Compute-intensive, latency-tolerant.
- Decode: Generate tokens one by one. Memory-bandwidth-intensive, latency-sensitive.
CS-4’s strategy: let each phase run on the hardware it was designed for.
┌─────────────────────────────────────────────────────────────────────────┐
│ Disaggregated Inference Pipeline │
├─────────────────────────────────────────────────────────────────────────┤
│ │
│ Step 1: Prefill │
│ ┌────────────────────────────────────────────────────────────────┐ │
│ │ AMD Helios / AWS Trainium / GPU Cluster │ │
│ │ Process input prompt → Compute KV cache → Prepare model state │ │
│ │ Characteristics: Compute-intensive, well-suited for GPU/ASIC │ │
│ └───────────────────────────┬────────────────────────────────────┘ │
│ │ │
│ │ Model state via RoCE v2 RDMA │
│ ▼ │
│ Step 2: Decode │
│ ┌────────────────────────────────────────────────────────────────┐ │
│ │ Cerebras CS-4 (3× WSE-3T) │ │
│ │ Receive model state → Ultra-low-latency decode → Generate │ │
│ │ Characteristics: Memory-bandwidth bound, SRAM advantage max │ │
│ │ Performance: > 4,400 Token/s/user (GPT-OSS-120B) │ │
│ └────────────────────────────────────────────────────────────────┘ │
│ │
│ Benefit: Prefill cluster is shared, decode cluster is dedicated │
│ Overall throughput improvement: up to 5x vs monolithic approach │
└─────────────────────────────────────────────────────────────────────────┘
Figure 6: Disaggregated Inference Pipeline — CS-4 focuses on latency-sensitive decode
The elegance of this architecture: customers don’t need to use expensive CS-4 cycles for compute-intensive but latency-tolerant prefill. Prefill can run on AMD Helios or AWS Trainium (lower cost), while CS-4 focuses on what it does best — ultra-low-latency decode.
4.2 What 4,400 Tokens/s Actually Means
Let’s put that number in perspective.
def analyze_token_speed(tokens_per_sec):
"""Analyze what token generation speed means in practice"""
# English: 1 token ≈ 0.75 words
english_words_per_sec = tokens_per_sec * 0.75
# Average human reading speed
avg_human_reading_wps = 5 # words/second (300 wpm)
# A 2000-word article
article_words = 2000
article_tokens = int(article_words / 0.75) # ~2667 tokens
cs4_time = article_tokens / tokens_per_sec
# Typical GPU: ~150 tokens/s
gpu_tokens_per_sec = 150
gpu_time = article_tokens / gpu_tokens_per_sec
print(f"CS-4 Token Generation Speed: {tokens_per_sec:,} tokens/s")
print(f"Equivalent: {english_words_per_sec:,.0f} words/s")
print(f"Human reading speed: {avg_human_reading_wps} words/s")
print(f"CS-4 / Human reading ratio: "
f"{english_words_per_sec / avg_human_reading_wps:.0f}x")
print()
print(f"2,000-word article generation time:")
print(f" CS-4: {cs4_time:.2f} seconds")
print(f" GPU: {gpu_time:.2f} seconds")
print(f" Speedup: {gpu_time / cs4_time:.0f}x")
analyze_token_speed(4400)
# Output:
# CS-4 Token Generation Speed: 4,400 tokens/s
# Equivalent: 3,300 words/s
# Human reading speed: 5 words/s
# CS-4 / Human reading ratio: 660x
#
# 2,000-word article generation time:
# CS-4: 0.61 seconds
# GPU: 17.78 seconds
# Speedup: 29x
CS-4 generates text 660x faster than a human can read it. By the time you’ve finished the first sentence of an AI response, the system could have generated an entire article.
For agentic AI systems, this speed is transformative. Cerebras CTO Sean Lie noted: “Being 30x faster doesn’t just make a response feel fast. It gives an agentic system room for more than an order of magnitude as much reasoning, verification, or tool use in the same wall-clock time.”
4.3 Throughput Per Watt: 10x Improvement Over CS-3
In AI infrastructure, peak FLOPs only tell part of the story. Performance per watt is what data center operators truly care about.
┌──────────────────────────────────────────────────────────────────────┐
│ Cerebras Throughput-Per-Watt Evolution │
│ │
│ Normalized Throughput/Watt │
│ ^ │
│ │ │
│ 10 │ ★ CS-4 (10x) │
│ │ / │
│ 8 │ / │
│ │ / │
│ 6 │ / │
│ │ / │
│ 4 │ / │
│ │ / │
│ 2 │ ★ CS-3 (1x) / │
│ │ / │
│ 1 │ ★ CS-2 / │
│ │ / │
│ 0 └───────────────────────────────────────────────────────────────► │
│ 2024 2025 2026 2027 2028 │
│ │
│ Drivers: ① Frequency doubled → more compute per watt │
│ ② Backpack power delivery → eliminated board losses │
│ ③ Direct liquid cooling → lower cooling overhead │
│ ④ I/O redesign → reduced interconnect power │
└──────────────────────────────────────────────────────────────────────┘
Figure 7: Cerebras Throughput-Per-Watt Evolution — CS-4 achieves 10x improvement
According to The Register’s estimates, the CS-4 draws approximately 120-140kW per rack — roughly half of what comparable AMD and NVIDIA rack systems consume. This means not only faster tokens, but cheaper tokens.
5. Code Examples: Programming the CS-4
5.1 Basic Inference with Cerebras SDK
import cerebras_pytorch as cb
import torch
from transformers import AutoTokenizer
# Initialize CS-4 runtime
# CS-4 automatically detects available WSE-3T devices
runtime = cb.Runtime(
backend="csx",
num_workers=3, # Leverage all 3 WSE-3T processors
precision="fp16_sparse", # Sparse FP16 for maximum throughput
)
# Load model and tokenizer
model_name = "gpt-oss-120b"
tokenizer = AutoTokenizer.from_pretrained(model_name)
# Model distribution across 3 wafers happens automatically
with runtime.device:
model = cb.AutoModelForCausalLM.from_pretrained(
model_name,
device_map="auto",
offload_strategy="sram", # Prefer on-wafer SRAM
trust_remote_code=True,
)
model.eval()
# Inference function with CS-4 optimizations
@cb.function
def generate_text(prompt: str, max_tokens: int = 1024):
inputs = tokenizer(prompt, return_tensors="pt")
with torch.no_grad():
outputs = model.generate(
inputs.input_ids,
max_length=inputs.input_ids.shape[1] + max_tokens,
do_sample=True,
temperature=0.7,
top_p=0.9,
pad_token_id=tokenizer.eos_token_id,
# CS-4 specific optimizations
use_cache=True,
num_beams=1,
repetition_penalty=1.1,
)
return tokenizer.decode(outputs[0], skip_special_tokens=True)
# Batch inference
prompts = [
"Explain the基本原理 of quantum computing",
"Write Python code for a real-time AI safety monitor",
"Analyze the global semiconductor market trends in 2026",
]
results = [generate_text(p) for p in prompts]
for i, (prompt, result) in enumerate(zip(prompts, results)):
print(f"=== Prompt {i+1} ===")
print(f"Input: {prompt[:50]}...")
print(f"Output: {result[:100]}...")
print(f"Latency: < 500ms (measured on CS-4)")
print()
5.2 Disaggregated Inference Configuration
# CS-4 Disaggregated Inference Setup
# Prefill on AMD Helios, Decode on CS-4
disaggregated_config = {
"prefill_engine": {
"type": "amd_helios",
"num_nodes": 4,
"precision": "bf16",
"max_batch_size": 64,
},
"decode_engine": {
"type": "cerebras_cs4",
"num_wafers": 3,
"precision": "fp16_sparse",
"max_batch_size": 1024,
},
"transfer": {
"protocol": "roce_v2", # RDMA over Converged Ethernet
"bandwidth_gbps": 2400, # Per-wafer I/O bandwidth
"latency_us": 2, # Wafer-to-wafer direct link
},
"pipeline": {
"prefill_chunk_size": 2048,
"kv_cache_offload": True,
"overlap_compute": True,
}
}
def start_disaggregated_inference(config):
print(f"Starting disaggregated inference service...")
print(f" Prefill engine: {config['prefill_engine']['type']} "
f"({config['prefill_engine']['num_nodes']} nodes)")
print(f" Decode engine: {config['decode_engine']['type']} "
f"({config['decode_engine']['num_wafers']} wafers)")
print(f" Transfer: {config['transfer']['protocol']} "
f"@ {config['transfer']['bandwidth_gbps']} Gbps")
print(f" Inter-wafer: {config['transfer']['latency_us']} μs")
print()
print("Expected performance:")
print(f" Time-to-first-token: < 50ms (prefill + transfer)")
print(f" Decode speed: > 4,400 tokens/s")
print(f" Throughput/watt: 10x vs CS-3")
return {"status": "ready", "endpoint": "grpc://cs4-cluster:50051"}
start_disaggregated_inference(disaggregated_config)
5.3 Performance Benchmarking
import time
import numpy as np
def benchmark_cs4_inference(model_name, batch_sizes, token_lengths):
"""
CS-4 inference performance benchmark
Simulates throughput across batch sizes and output lengths
Based on Cerebras published data (GPT-OSS-120B, sparse FP16)
"""
base_speed = 4400 # tokens/s at batch_size=1
results = []
for batch_size in batch_sizes:
for output_len in token_lengths:
# CS-4 batch efficiency scaling
if batch_size <= 4:
throughput = base_speed * batch_size * 0.95
elif batch_size <= 16:
throughput = base_speed * batch_size * 0.85
elif batch_size <= 64:
throughput = base_speed * batch_size * 0.70
else:
throughput = base_speed * batch_size * 0.50
latency = (output_len / throughput) * 1000 # ms
results.append({
"batch_size": batch_size,
"output_len": output_len,
"throughput_tps": throughput,
"latency_ms": latency,
"tokens_per_user": throughput / batch_size,
})
return results
# Run benchmark
benchmark = benchmark_cs4_inference(
model_name="gpt-oss-120b",
batch_sizes=[1, 4, 16, 64, 256],
token_lengths=[128, 512, 2048, 8192],
)
print(f"{'Batch':<8} {'Output':<8} {'Throughput':<15} {'Latency':<12} {'T/User':<12}")
print("-" * 55)
for r in benchmark:
print(f"{r['batch_size']:<8} {r['output_len']:<8} "
f"{r['throughput_tps']:<15.0f} {r['latency_ms']:<12.1f} "
f"{r['tokens_per_user']:<12.0f}")
6. Business Impact and Market Landscape
6.1 Financial Performance: Cloud Inference Up 287%
Cerebras went public in May 2026 at $185/share, raising $6.4 billion in the largest US tech IPO since Snowflake. The stock opened at $350 and closed the first day at $311.
As of August 18, 2026, the stock trades at $220 — down from its peak but still 42% above the IPO price. Q2 earnings revealed:
| Metric | Value | YoY Change |
|---|---|---|
| GAAP Revenue | $180.1M | +74% |
| Core Revenue | $209.9M | +103% |
| Cloud Inference Revenue | $127.7M | +287% |
| Hardware Revenue | $54.1M | -23% |
| GAAP Net Loss | $450.5M | — |
| RPO (Remaining Performance Obligations) | $25.4B | — |
The standout number is cloud inference revenue growing 287% YoY to $127.7M. This signals explosive demand for “fast inference” as a service. Meanwhile, hardware revenue declined 23%, indicating Cerebras is transitioning from a hardware vendor to a cloud services provider.
6.2 Competitive Landscape: Cerebras vs NVIDIA vs AMD
┌─────────────────────────────────────────────────────────────────────────┐
│ AI Inference Market Landscape (Q3 2026) │
├─────────────────────────────────────────────────────────────────────────┤
│ │
│ High-Performance Inference │ General Inference │ Edge Inference │
│ ┌──────────────────────┐ │ ┌─────────────────┐ │ ┌──────────────┐ │
│ │ Cerebras CS-4 │ │ │ NVIDIA B200 │ │ │ Qualcomm │ │
│ │ 4,400 Token/s │ │ │ ~150 Token/s │ │ │ AI Engine │ │
│ │ 30x faster │ │ │ HBM3e 192GB │ │ │ On-device │ │
│ │ 50T+ params │ │ │ General purpose │ │ │ Low power │ │
│ └──────────┬───────────┘ │ └─────────────────┘ │ └──────────────┘ │
│ │ │ │ │
│ ▼ │ │ │
│ ┌──────────────────────┐ │ ┌─────────────────┐ │ │
│ │ AMD Helios │ │ │ AWS Trainium2 │ │ │
│ │ (CS-4 partner) │ │ │ (CS-4 partner) │ │ │
│ │ Prefill engine │ │ │ Prefill engine │ │ │
│ └──────────────────────┘ │ └─────────────────┘ │ │
│ │
│ Key Differentiator: │
│ Cerebras doesn't compete head-on with NVIDIA across the board │
│ Instead, it focuses on decode inference and partners for prefill │
│ Disaggregated inference is becoming the new standard │
└─────────────────────────────────────────────────────────────────────────┘
Figure 8: AI Inference Market Landscape — Cerebras shifts from “challenger” to “niche leader”
Cerebras’s competitive strategy is clear: don’t be a full NVIDIA replacement; be the inference accelerator. The partnerships with AMD Helios and AWS Trainium reveal a company building an ecosystem where CS-4 handles latency-sensitive decode while other hardware handles compute-intensive prefill.
6.3 Customer Ecosystem
At the CS-4 launch, Cerebras disclosed the following customers and partners:
- OpenAI: GPT-5.6 Sol inference partner, achieving 750 tokens/s on Cerebras
- G42: UAE-based AI leader, Cerebras’s largest customer (~86% of 2025 revenue)
- AMD: Helios + CS-4 disaggregated inference partnership, production in Q4 2026
- AWS: Trainium + CS-4 disaggregated inference on Amazon Bedrock, expected Q1 2027
- CrowdStrike: Inline security detection using CS-4 — a completely new application category
- Cognition, Lovable, Block, Figma, GSK: Agentic AI workloads across finance, life sciences, and developer tools
7. Conclusion: The Speed Revolution
The Cerebras CS-4 proves several important propositions:
- Wafer-scale computing is commercially viable. Not a proof-of-concept, but a shippable, deployable, profitable product.
- SRAM beats DRAM for inference. The bandwidth and latency advantages are decisive in the decode phase.
- System architecture matters more than chip design. The Backpack power delivery, Nexus modular platform, and switch-free topology are the true innovations.
- Disaggregated inference is the future. Let specialized hardware do what it does best — heterogeneous computing is back in the mainstream.
Andrew Feldman told Reuters the company expects to be “four times as fast by the end of 2027, with 20x more throughput.” The CS-5 is already on the roadmap.
But the bigger picture is this: AI inference is evolving from “can it run?” to “how fast can it run?” When token generation outpaces human reading speed, when agents can complete multi-step reasoning in milliseconds, the product landscape for AI applications will fundamentally change.
The CS-4 is the first foundation stone of that new era. It proves a simple truth: in the world of AI, speed is everything.
Sources: Cerebras Official Blog, GlobeNewswire, The Next Web, Converge Digest, Cerebras Q2 2026 Earnings Release, The Register, SemiAnalysis