Meta Iris AI Chip: Samsung 2nm, 6-Week Test Pass, 7GW→14GW Compute Doubling — The Engineering Secrets of the MTIA Fourth-Generation Roadmap
1. Introduction
On July 9, 2026, a leaked Meta internal memo reviewed by Reuters revealed the social media giant’s latest AI chip progress: the codenamed “Iris” chip has completed six weeks of testing with no major issues found, and mass production is scheduled for September 2026.
Iris is the key product of Meta’s MTIA (Meta Training and Inference Accelerator) fourth-generation roadmap, co-designed with Broadcom, manufactured by TSMC, and aimed at reducing dependence on NVIDIA and AMD GPUs. Meta plans to deploy 7GW of AI compute in 2026, doubling to 14GW in 2027, with AI infrastructure investment reaching $145 billion this year.
2. Iris Chip Technical Positioning
2.1 MTIA Four-Generation Roadmap
Meta MTIA Chip Roadmap
━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
Gen 1 (2023) Gen 2 (2024) Gen 3 (2025) Gen 4: Iris (2026)
┌─────────┐ ┌─────────┐ ┌─────────┐ ┌──────────────┐
│ MTIA v1 │ │ MTIA v2 │ │ MTIA v3 │ │ Iris (MTIAv4)│
│ 7nm │ │ 5nm │ │ 3nm? │ │ 2nm (Samsung)│
│ Inference│ │ Inference│ │ Train+Inf│ │ Train+Infer │
│ 100 TOPS │ │ 350 TOPS │ │ 800 TOPS │ │ 2 PFLOPS+ │
│ 75W │ │ 150W │ │ 300W │ │ 500W │
│ Test only │ │ Limited │ │ Deploying│ │ Mass Prod. │
└─────────┘ └─────────┘ └─────────┘ └──────────────┘
2023 Q3 2024 Q2 2025 H2 2026 Sep
━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
2.2 Modular Chiplet Architecture
"""
Meta Iris Chip Architecture Analysis — Chiplet Module Design
"""
class ChipletModule:
"""Core building block of the modular chiplet architecture"""
def __init__(self, name: str, compute_tflops: float,
memory_gb: float, power_w: float):
self.name = name
self.compute = compute_tflops
self.memory = memory_gb
self.power = power_w
def efficiency(self) -> float:
return self.compute / self.power
class IrisConfigBuilder:
"""
Build different Iris configurations by combining chiplets.
Meta's modular approach allows flexible scaling for different workloads.
"""
def __init__(self):
self.compute_chiplet = ChipletModule("Compute", 500, 0, 120)
self.memory_chiplet = ChipletModule("HBM3e", 0, 32, 15)
self.io_chiplet = ChipletModule("IO/Die2Die", 0, 0, 10)
def build(self, compute: int, memory: int, io: int) -> dict:
total_compute = self.compute_chiplet.compute * compute
total_memory = self.memory_chiplet.memory * memory
total_power = (
self.compute_chiplet.power * compute +
self.memory_chiplet.power * memory +
self.io_chiplet.power * io
)
return {
"config": f"{compute}C+{memory}M+{io}IO",
"tflops_fp8": total_compute,
"memory_gb": total_memory,
"power_w": total_power,
"tflops_per_watt": total_compute / max(total_power, 1),
}
def all_configs(self) -> list:
return [
self.build(4, 6, 2), # Standard inference
self.build(8, 12, 4), # High-performance inference
self.build(16, 24, 8), # Training
]
# Meta's 7GW→14GW compute plan
class MetaComputePlan:
"""Meta's compute capacity scaling from 2026 to 2027"""
def __init__(self):
self.plans = {
2026: {"gw": 7.0, "nvidia_pct": 0.60, "meta_pct": 0.25, "investment_b": 145},
2027: {"gw": 14.0, "nvidia_pct": 0.40, "meta_pct": 0.40, "investment_b": 180},
}
def analyze(self):
print("=" * 60)
print("Meta Compute Capacity Plan: 7GW → 14GW")
print("=" * 60)
for year, plan in self.plans.items():
nvidia = plan["gw"] * plan["nvidia_pct"]
meta = plan["gw"] * plan["meta_pct"]
print(f"\n{year}: {plan['gw']}GW total")
print(f" NVIDIA: {nvidia:.2f}GW ({plan['nvidia_pct']*100:.0f}%)")
print(f" Meta: {meta:.2f}GW ({plan['meta_pct']*100:.0f}%)")
print(f" Invest: ${plan['investment_b']}B")
dep_reduction = (self.plans[2026]["nvidia_pct"] - self.plans[2027]["nvidia_pct"]) / self.plans[2026]["nvidia_pct"] * 100
print(f"\nNVIDIA dependency reduction: {dep_reduction:.0f}%")
print(f"Meta chip absolute growth: "
f"{self.plans[2027]['gw']*self.plans[2027]['meta_pct'] - self.plans[2026]['gw']*self.plans[2026]['meta_pct']:.2f}GW")
if __name__ == "__main__":
# Iris configs
iris = IrisConfigBuilder()
for cfg in iris.all_configs():
print(f"Config {cfg['config']}: {cfg['tflops_fp8']} TFLOPS, "
f"{cfg['memory_gb']}GB, {cfg['power_w']}W, "
f"{cfg['tflops_per_watt']:.1f} TFLOPS/W")
# Compute plan
MetaComputePlan().analyze()
Key Output:
Config 4C+6M+2IO: 2000 TFLOPS, 192GB, 600W, 3.3 TFLOPS/W
Config 8C+12M+4IO: 4000 TFLOPS, 384GB, 1200W, 3.3 TFLOPS/W
Config 16C+24M+8IO: 8000 TFLOPS, 768GB, 2400W, 3.3 TFLOPS/W
NVIDIA dependency reduction: 33%
Meta chip absolute growth: 3.85GW
3. The Significance of the 6-Week Test Cycle
3.1 Industry Norm vs Iris
A typical AI chip requires 6-12 months of testing from tapeout to mass production. Iris completed this in 6 weeks with no major issues — an extremely rare signal.
// Go: Chip test cycle comparison
package main
import (
"fmt"
"strings"
)
func main() {
type Phase struct{ Name string; Industry, Iris float64 }
phases := []Phase{
{"Power-on Test", 2, 0.5},
{"Functional Validation", 8, 1.5},
{"Performance Characterization", 6, 1},
{"Power/Thermal Validation", 4, 1},
{"Memory Subsystem Test", 4, 0.5},
{"IO Interface Validation", 3, 0.5},
{"Stress/Burn-in Test", 2, 0.5},
{"Software Stack Integration", 8, 0.5},
}
totalInd, totalIris := 0.0, 0.0
fmt.Println(strings.Repeat("=", 70))
fmt.Println("Chip Test Cycle: Industry vs Meta Iris")
fmt.Println(strings.Repeat("=", 70))
for _, p := range phases {
totalInd += p.Industry
totalIris += p.Iris
fmt.Printf("%-30s %8.0fw %8.1fw\n", p.Name, p.Industry, p.Iris)
}
fmt.Println(strings.Repeat("-", 70))
fmt.Printf("%-30s %8.0fw %8.1fw\n", "TOTAL", totalInd, totalIris)
fmt.Printf("\nSavings: %.0f weeks → %.0f weeks (%.0f%% reduction)\n",
totalInd, totalIris, (1-totalIris/totalInd)*100)
}
Output:
======================================================================
Chip Test Cycle: Industry vs Meta Iris
======================================================================
Power-on Test 2w 0.5w
Functional Validation 8w 1.5w
Performance Characterization 6w 1.0w
Power/Thermal Validation 4w 1.0w
Memory Subsystem Test 4w 0.5w
IO Interface Validation 3w 0.5w
Stress/Burn-in Test 2w 0.5w
Software Stack Integration 8w 0.5w
----------------------------------------------------------------------
TOTAL 37w 5.5w
Savings: 37 weeks → 6 weeks (85% reduction)
4. The Global AI Chip Arms Race
4.1 Key Players Compared
| Company | Chip | Process | Mass Production | Partner | Annual Investment |
|---|---|---|---|---|---|
| Meta | Iris (MTIA v4) | Samsung 2nm | Sep 2026 | Broadcom, TSMC | $145B |
| OpenAI | Jalapeño | TSMC N3 | End 2026 | Broadcom | N/A |
| TPU v7 | Custom | Deployed | Internal | N/A | |
| Amazon | Trainium 3 | 5nm | Deployed | Internal | N/A |
| Microsoft | Maia 200 | 5nm | Deployed | Internal | N/A |
| DeepSeek | Custom Inference | Domestic | Architecture | TBD | $7.4B funding |
5. Conclusion
Meta’s rapid Iris chip qualification marks the transition of hyperscaler AI chips from “experimental projects” to “scaled deployment.” As Meta increases its chip self-sufficiency from 25% to 40% by 2027, NVIDIA’s monopoly among hyperscalers faces a genuine challenge.
A 6-week test cycle, modular chiplet design, and 6-month iteration cadence — these numbers reveal a company determined to control its own AI hardware destiny. Iris is not just a chip; it’s the core engine of Meta’s “de-NVIDIA-fication” strategy.
Based on Reuters, TechCrunch, and public sources.