478x Faster Than A100 at 1/24th the Power! Peking University's Phase-Change Memristor Neural Dynamics Chip in Science: Turning a "Storage Defect" into a Computing Advantage
Introduction: When Computers Finally “Keep Up” with the Brain
The human brain processes billions of parallel electrical signals across neurons and synapses every moment. A simple thought involves an extraordinarily complex neural dynamics process. Yet when computers attempt to simulate real-time cortical activity, latency has always been the Achilles’ heel—like a live stream buffering. In scenarios like neurosurgical navigation or brain-computer interface closed-loop control, even tens of milliseconds of delay can be fatal.
On July 3, 2026, Professor Yuchao Yang’s team at Peking University’s School of Integrated Circuits, in collaboration with researcher Zhitang Song’s team at the Chinese Academy of Sciences’ Shanghai Institute of Microsystem and Information Technology, published a groundbreaking paper in Science titled “A sub-10-millisecond neural dynamical system based on phase change memristors.” They fabricated a neural dynamics chip based on phase-change memristors at a mature 40nm process node, compressing the single-step computation latency of neural dynamical systems to 2.12 milliseconds—for the first time pushing this field into the millisecond era.
The key performance metrics are staggering: in brain cortex high-fidelity reconstruction tasks, this chip—occupying only 0.28mm²—achieved a 50-to-478x speedup over an NVIDIA A100 GPU, while reducing power consumption by 11-to-24x. Even more remarkable, the chip uses a mature 40nm process, requiring no advanced lithography—mass production is feasible on domestic Chinese fabs.
The deeper significance of this work extends far beyond impressive benchmark numbers. It pioneered a new paradigm by transforming a long-considered “defect” of phase-change memory—conductance drift—into the core driving force of computation. Science published a dedicated Perspective article alongside this work, praising it as “representing a paradigm shift toward physics-driven computing.”
I. The Memory Wall: A Half-Century Nightmare for Neural Dynamics
1.1 What is a Neural Dynamical System?
A neural dynamical system elegantly integrates the learning capability of neural networks with the continuous dynamic evolution of differential equations. It can reconstruct smooth, precise 3D structures from incomplete, noisy data, excelling at tasks such as surface reconstruction, dynamic modeling, and continuous field estimation.
Mathematically, the core of a neural dynamical system is a Neural ODE:
dh(t)/dt = f(h(t), t, θ)
where h(t) is the system state, f is the derivative function parameterized by a neural network, and θ represents the network weights. Solving this equation requires repeated numerical integration, with step size adjustment at each step—too large a step causes divergence, too small a step causes computational explosion.
1.2 The von Neumann Bottleneck: The Memory Wall
In traditional computer architecture, memory (DRAM/SRAM) and processors (CPU/GPU) are separated. The massive intermediate variables generated during neural dynamics system solving must be shuttled back and forth between memory and processor.
┌─────────────────────────────────────────────────────────────┐
│ The von Neumann Memory Wall Problem │
│ │
│ ┌──────────┐ Data Movement (70% power) ┌──────────┐ │
│ │ CPU/ │ ◄══════════════════════════► │ DRAM │ │
│ │ GPU │ Bus Bandwidth Bottleneck │ (Memory) │ │
│ └──────────┘ └──────────┘ │
│ │ ▲ │
│ │ ▲ Read weights, read state │ │
│ ▼ │ Write intermediates, new step │ │
│ ┌───────────────────────────────────────────┘ │
│ │ Each step requires: │
│ │ ① Read weight matrix from DRAM → high bandwidth │
│ │ ② Read current state from DRAM → low latency │
│ │ ③ CPU/GPU matrix multiply → computation │
│ │ ④ Write intermediate results → bandwidth │
│ │ ⑤ Check step quality → loop ①~④ │
│ │ ⑥ Adjust step size → repeat ①~⑤ │
│ └─────────────────────────────────────────────────────────┘
│ │
│ Result: >70% of power wasted on data movement, not compute │
│ Single-step latency amplified by bus + memory access │
└─────────────────────────────────────────────────────────────┘
This is the memory wall problem that has plagued neural dynamical systems for half a century—under the von Neumann architecture, computational efficiency is fundamentally locked by data movement overhead.
II. Turning Defects into Weapons: The “Controlled In-Memory Computing” Revolution
2.1 Phase-Change Memory (PCM) Fundamentals
Phase-change memory uses reversible phase transitions between crystalline (low resistance) and amorphous (high resistance) states in chalcogenide compounds to store data. By applying electrical pulses of different intensities and durations, the degree of crystallization can be precisely controlled, enabling multi-level resistance states.
However, PCM has a long-considered “defect”—conductance drift. The conductance value changes predictably over time, traditionally causing data read errors in digital storage applications. For the past two decades, engineers have invested heavily in suppressing this characteristic.
2.2 The Genius Insight: Let Physics “Compute” Itself
The breakthrough insight from Yang’s team was this: since conductance drift is regular, predictable, and controllable, why not directly use it for computation?
The most time-consuming step in neural dynamical systems is adaptive step size search—repeatedly trying, comparing, and deciding how large the next integration step should be. Traditional solutions use digital circuits (comparators, counters, multipliers, adders), requiring multiple rounds of data reads, computations, and writes.
The team’s “Controlled In-Memory Computing” paradigm encodes the integration step size directly as the conductance state of PCM cells, allowing the device’s own physical evolution to perform the step search:
┌─────────────────────────────────────────────────────────────┐
│ Controlled In-Memory Computing: Physics-Driven Step Search│
│ │
│ Traditional (Digital Circuit): │
│ ┌──────────┐ ┌──────────┐ ┌──────────┐ │
│ │ Read │───►│ Compare+ │───►│ Update │ │
│ │ Step+Err │ │ Compute │ │ Step Val │ │
│ └──────────┘ └──────────┘ └──────────┘ │
│ │ │ │ │
│ ▼ ▼ ▼ │
│ 3 memory accesses + 5 operations per iteration │
│ Area: ~1mm² │
│ │
│ PKU Solution (Physics-Driven): │
│ ┌──────────────────────────────────────────────┐ │
│ │ Phase-Change Memory Array │ │
│ │ │ │
│ │ G(t) = G₀ · (t/t₀)^(-ν) (drift law) │ │
│ │ │ │
│ │ When conductance drifts to threshold → auto-switch │ │
│ │ No reads, no writes, no data movement │ │
│ │ Material physics completes step search automatically │ │
│ └──────────────────────────────────────────────┘ │
│ │
│ Area compressed to 0.28mm² (<1/3 of traditional) │
│ Zero additional power for step search │
└─────────────────────────────────────────────────────────────┘
The physical law governing conductance drift is:
G(t) = G₀ · (t/t₀)^(-ν)
where G₀ is the initial conductance, t₀ is the reference time, and ν is the drift coefficient. The team precisely controlled ν through carbon doping, enabling the drift speed and direction to be tuned according to design requirements. When a larger step is needed, resistance is programmed to one value; when a smaller step is needed, to another. The material “feels its way” through the computation, completing step size search that would require extensive digital logic.
2.3 Dual Functionality: Same Array for Storage and Computation
Even more ingeniously, the team mapped both weight storage and matrix operations of the neural network onto the same PCM array. Each row stores one neuron’s weight vector. By applying input voltages to the columns and reading output currents, the matrix multiplication result is obtained directly—this is called In-Memory Multiply-Accumulate (In-Memory MAC).
┌─────────────────────────────────────────────────────────────┐
│ Dual-Function PCM Array Design │
│ │
│ ┌─────┬─────┬─────┬─────┬─────┐ │
│ │W₁₁ │W₁₂ │W₁₃ │... │W₁ₙ │ ← Row 1: Weight Vector 1 │
│ ├─────┼─────┼─────┼─────┼─────┤ │
│ │W₂₁ │W₂₂ │W₂₃ │... │W₂ₙ │ ← Row 2: Weight Vector 2 │
│ ├─────┼─────┼─────┼─────┼─────┤ │
│ │W₃₁ │W₃₂ │W₃₃ │... │W₃ₙ │ ← Row 3: Weight Vector 3 │
│ ├─────┼─────┼─────┼─────┼─────┤ │
│ │... │... │... │... │... │ ← Drift Row │
│ ├─────┼─────┼─────┼─────┼─────┤ │
│ │Wₘ₁ │Wₘ₂ │Wₘ₃ │... │Wₘₙ │ ← Row m: Weight Vector m │
│ └─────┴─────┴─────┴─────┴─────┘ │
│ │ │ │ │ │
│ ▼ ▼ ▼ ▼ │
│ Input Voltage Vector V = [v₁, v₂, v₃, ..., vₙ] │
│ │
│ Output Current Iⱼ = Σᵢ Gⱼᵢ · Vᵢ (Kirchhoff's Current Law) │
│ ↑ This is the physical realization of W·V! │
│ │
│ Weight Storage + Matrix Multiply = Same Array, One Pass │
│ Step Drift + Weight Matrix = Same Array, No Interference │
└─────────────────────────────────────────────────────────────┘
This means: weights don’t need to be read out, matrix multiplication needs no extra circuits, and step search requires no digital logic. Three of the most expensive operations are all “packaged” into the physical system of the PCM array.
III. Chip Architecture and Technical Details
3.1 Core Specifications
| Parameter | Value |
|---|---|
| Process Node | 40nm CMOS |
| Core Array Area | 0.28 mm² |
| Operating Frequency | 50 MHz |
| Single-Step Latency | 2.12 ms |
| Pipeline Stages | 9 |
| Resistance Levels | 16 (differential: ±8) |
| Write/Erase Endurance | 10¹⁰ cycles |
| Operating Temperature | 0°C ~ 70°C |
| Material | Carbon-doped chalcogenide |
3.2 Nine-Stage Pipeline Architecture
The chip employs a 9-stage pipeline architecture:
┌─────────────────────────────────────────────────────────┐
│ 9-Stage Pipeline Microarchitecture │
│ │
│ Stage 1: Input Encoding → Voltage Vector Generation │
│ Stage 2: Array Read → In-Memory MAC Computation │
│ Stage 3: Current Sampling→ ADC Conversion │
│ Stage 4: Activation Func → Nonlinear Mapping │
│ Stage 5: State Update → h(t+Δt) Computation │
│ Stage 6: Error Estimation→ Step Quality Assessment │
│ Stage 7: Conductance Drift→ Physical Step Adaptation │
│ Stage 8: Time Interleave → Wear-Leveling Scheduling │
│ Stage 9: Result Output → External Interface │
└─────────────────────────────────────────────────────────┘
Stage 7 is the core innovation: step size adjustment is performed not by digital logic, but by the physical conductance drift of PCM cells.
IV. Performance Benchmark: Brain Cortex Reconstruction
4.1 Benchmark: 3D Cortex Reconstruction
The most rigorous test was 3D surface reconstruction of the brain’s gray and white matter. The traditional FreeSurfer tool on a 16-core server takes 2.5 hours. A standard GPU running the same neural dynamics algorithm requires about 2 seconds.
| Solution | Time | Gray Matter Error | White Matter Error |
|---|---|---|---|
| FreeSurfer (16-core CPU) | ~2.5 hours | ~0.3mm | ~0.4mm |
| NVIDIA A100 GPU | ~1.98 sec | 0.26mm | 0.39mm |
| PKU Chip | 426 ms | 0.245mm | 0.376mm |
The PKU chip is not only 4.6x faster than A100 in this task (peak 478x in specific scenarios), but also achieves lower reconstruction error. The generated surface is smooth, closed, and topologically consistent.
4.2 Benchmark: 3D Manifold Mesh Generation
| Metric | vs ASIC | vs A100 GPU |
|---|---|---|
| Speedup | 3.82× ~ 36.27× | 50.38× ~ 478.18× |
| Power Reduction | 11.75× ~ 24.73× | - |
| Energy per Task | ~1/1000 of phone charge | - |
V. Industry Landscape and Future Outlook
5.1 Technology Comparison
| Approach | Representative | Process | Core Advantage | Limitation |
|---|---|---|---|---|
| Traditional GPU | NVIDIA A100 | 7nm | General purpose | Memory wall, high power |
| SRAM IMC | Mythic | 28nm | Fast | Low density, high cost |
| RRAM IMC | Multiple startups | 28-22nm | Low mfg cost | Reliability concerns |
| PCM IMC | PKU Chip | 40nm | Physics-driven, ultra-low power | Specialized domain |
5.2 From Lab to Clinic
The path from academic paper to clinical application requires:
- Engineering → Mass production, system integration, software stack
- Clinical Validation → Prospective clinical studies (2-3 years)
- Regulatory Approval → NMPA/FDA clearance for novel computing hardware
- Supply Chain → PCM material, fab, packaging, testing maturity
5.3 Roadmap
2026 ──── Prototype Validation (Science publication)
│
2027-2028 ── Small-scale production + Research labs
│ ┌ BCI prototype systems
│ ├ Neurosurgical navigation prototypes
│ └ Neurodegenerative disease research platforms
│
2029-2031 ── Clinical validation + Medical device integration
│ ┌ Navigation products
│ ├ Portable brain imaging devices
│ └ DBS parameter optimization
│
2032+ ──── Large-scale clinical adoption + Extended scenarios
┌ Consumer BCI
├ Embodied AI edge computing
└ Real-time digital twin simulation
VI. Conclusion
This breakthrough by Yang’s team represents a fundamental shift in computing paradigm:
-
From “Suppressing Defects” to “Exploiting Defects”: Conductance drift, long considered a reliability issue, becomes a step-size search engine—deeper than any algorithmic optimization.
-
From “Digital Computing” to “Physical Computing”: Instead of repeatedly computing step sizes with digital circuits, the material’s physical evolution does it automatically. Computation is no longer a logical simulation of physics—physics itself participates in the computation.
-
From “Separated Memory and Compute” to “In-Memory Computing”: 0.28mm² that simultaneously performs weight storage, matrix multiplication, and step search—three of the most expensive operations “packaged” into one physical system.
References
- Cai et al., “A sub-10-millisecond neural dynamical system based on phase change memristors”, Science, 2026
- Peking University Official Report, 2026-07-06
- DeepTech, “First Controlled In-Memory Computing! Memristor Neural Dynamics Chip Unveiled”, 2026-07-05
- Guangming Daily, PCM Breakthrough Report, 2026-07-04